UST926012I4

ABSTRACT

A DEVICE IS DISCLOSED WHICH ALLOWS A PROCESSOR TO INITIATE A START 1/0 OPERATION WITHOUT WAITING FOR THE COMPLETION OF THE CONNECTION BETWEEN THE CHANNEL AND THE DESIRED INPUT/OUTPUT (I/0) UNIT. IN THE EVENT THAT THE I/O INTERFACE IS BUSY THE PROCESSOR IS RELEASED AND THE START I/O INSTRUCTION IS QUEUED IN THE CHANNEL UNTIL THE I/O INTERFACE BECOMES AVAILABLE AT WHICH TIME THE START I/O INSTRUCTION IS AGAIN INITATED WITHOUT PROCESSOR INTERACTION. WHENEVER AN I/O INTERFACE BECOMES AVAILABLE, THE   QUEUED INSTRUCTIONS ARE POLLED TO DETERMINE IF ONE HAS BEEN QUEUED FOR THE PARTICULAR UNIT. A PRIORITY MEANS IS INCLUDED WHICH CAUSES THE QUEUED INSTRUCTIONS TO BE REINITIATED IN A FIFO ORDER.



